The technology described herein relates to display controllers for data processing systems.
In data processing systems, an image that is to be displayed to a user is processed by the data processing system for display. The image for display is typically processed by a number of processing stages before it is displayed to the user. For example, an image will be processed by a so called “display controller” of a display for display.
Typically, the display controller will read an output image to be displayed from a so called “frame buffer” in memory which stores the image as a data array (e.g. by internal Direct Memory Access (DMA)) and provide the image data appropriately to the display (e.g. via a pixel pipeline) (which display may, e.g., be a screen or printer). The output image is stored in the frame buffer in memory, e.g. by a graphics processor, when it is ready for display and the display controller will then read the frame buffer and provide the output image to the display for display.
The display controller processes the image from the frame buffer to allow it to be displayed on the display. This processing includes appropriate display timing functionality (e.g. it is configured to send pixel data to the display with appropriate horizontal and vertical blanking periods), to allow the image to be displayed on the display correctly.
Many electronic devices and systems use and display plural windows (or surfaces) displaying information on their display screen, such as video, a graphical user interface, etc. One way of providing such windows is to use a compositing window system, in which individual input windows (surfaces) are combined appropriately (i.e. composited) and the result is written out to the frame buffer, which is then read by the display controller for display.
It is also possible to combine the functions of the compositing system into a display controller, e.g. to provide a compositing display controller. In this case, individual input windows (surfaces) are read and combined appropriately (i.e. composited) by the display controller, and then a combined (composited) surface is provided for display by the display controller. This can reduce the number of read and write operations to external memory and thereby the power and memory bandwidth of the overall data processing system.
It is becoming increasingly common for electronic devices and systems to be configured so as to be able to provide output images for display on plural display devices. It may be desired, for example, to provide output images to the system's local display (such as a display panel) and to an external display. The output images provided to the two displays may be the same, or may differ, for example the external display may require and use a different resolution and/or aspect ratio to the local display.
FIG. 1 shows schematically the operation of a conventional dual-display compositing media processing system in a so called “clone” mode of operation, wherein corresponding content is displayed on both a primary (e.g. local) and secondary (e.g. external) display. Plural input surfaces or layers (e.g. 1-4) are generated, and stored in main memory 1. The stored input surfaces are each read by the primary display processor 2, combined (composited) to generate a composited output surface (frame), and then displayed on the primary display 3. Similarly, the stored input surfaces are each read by a secondary display processor 4, combined (composited) to generate a composited output surface (frame), and then displayed on the secondary display 5.
The main memory 1 of the system is typically external to the display controller(s). The reading of data from and writing data to the main memory 1 (e.g. frame buffer) can therefore consume a relatively significant amount of power and memory bandwidth.
The Applicants' earlier application GB-A-2524359 describes a technique that can be used to reduce the number of read and write operations required for the so-called “clone” mode (and thereby the power and memory bandwidth) by providing a display controller with a write out stage operable to write an output surface to external memory. FIG. 2 shows schematically the operation of the display controller of GB-A-2524359.
As shown in FIG. 2, plural input surfaces or layers (e.g. Layers 1-4) are again generated, and stored in main memory 1. The stored input surfaces are each read by the primary display processor 2, combined (composited) to generate a composited output surface (frame), and then displayed on the primary display 3. However, rather than the secondary display processor 4 also reading each of the stored input surfaces for composition, the combined (composited) surface generated by the primary display processor 2 is instead written to main memory 1. The secondary display processor 4 then reads the composited surface from main memory 1, optionally processes (e.g. scales or rotates) the surface for display, and then provides the surface for display on the secondary (e.g. external) display 5.
Accordingly, only one write operation to the main memory 1 and one read operation from the main memory 1 is required for the dual-display operation in “clone” mode (i.e. after the plural input surfaces have been read). Accordingly, the memory bandwidth and power consumption is reduced compared with the conventional arrangements.
Notwithstanding this, the Applicants believe that there remains scope for improvements to display controllers.
Like reference numerals are used for like components throughout the drawings, where appropriate.